Title

Packet-Mode Asynchronous Scheduling Algorithm for Partially Buffered Crossbar Switches View Document

Document Type

Presentation

Presentation Date

12-2009

Conference Name

IEEE Global Telecommunications Conference

Conference Location

Honolulu, Hawaii

Source of Publication

IEEE Global Telecommunications Conference, 2009. GLOBECOM 2009

Publisher

IEEE

Peer Review

Yes

Abstract

Traditional crossbar switches use centralized scheduling algorithms with high time complexity. In contrast, buffered crossbar switches are capable of distributed scheduling due to crosspoint buffers, which decouple the dependency between inputs and outputs. However, crosspoint buffers are expensive on-chip memories. To reduce the hardware cost of buffered crossbar switches and make them scalable, we consider partially-buffered crossbar switches, whose crosspoint buffers can be of an arbitrarily small size and store only part of a packet instead of the entire packet. In this paper, we propose the Packet-mode Asynchronous Scheduling Algorithm (PASA) for partially buffered crossbar switches. PASA combines the features of both distributed and centralized scheduling algorithms. It works in an asynchronous mode and can directly handle variable length packets without Segmentation And Reassembly (SAR). We theoretically prove that, with a speedup of two, PASA achieves 100% throughput for any admissible traffic. We also show that outputs in PASA have a large probability to avoid the more time-consuming centralized scheduling process, and thus make fast scheduling decisions. Finally, we present simulation data to verify the analytical results and evaluate the performance of PASA.

Keywords

segmentation and reassembly, packet-mode asynchronous scheduling algorithm, partially buffered crossbar switches, centralized scheduling algorithms, distributed scheduling, crosspoint buffers, on-chip memories, hardware cost reduction, telecommunication switching, buffer storage, packet radio networks, scheduling, Scheduling algorithm, Packet switching, Switches, Buffer storage, Hardware, Costs, Throughput, Traffic control, Analytical models, Performance analysis

Disciplines

Computer Sciences

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Link to Original Published Item

http://ieeexplore.ieee.org/document/5425406/