An Efficient Implementation of SHA-1 Hash Function
2006 IEEE International Conference on Electro/information Technology
East Lansing, MI
Source of Publication
Electro/information Technology, 2006 IEEE International Conference on
The latest cryptographical application demands in a typical embedded system demand both high speed and small area. Hash function has been widely used in the digital signature, message authentication. In this paper, a new area efficient SHA-1 implementation is proposed. The proposed design was captured using VHDL hardware language and also implemented on Xilinx FPGA. The correctness of the functionality has been verified using simulation tools and the test vectors. A comparison between the proposed SHA-1 hash function implementation with other related works show that it occupies very small area while also achieving a high throughput, thus it could be adopted in an embedded system where area constraint is a concern
embedded system, SHA-1 hash function, VHDL hardware language, Xilinx FPGA, hardware description languages, cryptography, embedded systems, field programmable gate arrays, Cryptography, Authentication, Algorithm design and analysis, Security, Hardware, Turning, Protection, Portable computers, Emulation, Manufacturing
Guoping Wang Dr. (2006).
An Efficient Implementation of SHA-1 Hash Function. Electro/information Technology, 2006 IEEE International Conference on. IEEE.Presented at 2006 IEEE International Conference on Electro/information Technology, East Lansing, MI.
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