Title

The Efficient Implementation of An Array Multiplier

Document Type

Presentation

Presentation Date

5-2005

Conference Name

2005 IEEE International Conference on Electro and Information Technology

Conference Location

Lincoln, NE

Source of Publication

Electro Information Technology, 2005 IEEE International Conference on

Publisher

IEEE

Abstract

Multiplication is one of the basic and critical operations in the computations. Efficient implementations of multipliers are required in many applications. In this paper, a new implementation of the array multiplier for unsigned numbers is proposed which significantly reduces the silicon area compared to recently published array multiplier while with no penalty of speed and power. The proposed scheme is applicable for VLSI and FPGA application and it can be easily extended to signed number computations.

Keywords

signed number computations, array multiplier, unsigned numbers, VLSI application, FPGA application, multiplying circuits, Very large scale integration, Silicon compounds, Neural networks, Field programmable gate arrays, Tree data structures, Encoding, Wires

Disciplines

Engineering

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