The Efficient Implementation of An Array Multiplier
2005 IEEE International Conference on Electro and Information Technology
Source of Publication
Electro Information Technology, 2005 IEEE International Conference on
Multiplication is one of the basic and critical operations in the computations. Efficient implementations of multipliers are required in many applications. In this paper, a new implementation of the array multiplier for unsigned numbers is proposed which significantly reduces the silicon area compared to recently published array multiplier while with no penalty of speed and power. The proposed scheme is applicable for VLSI and FPGA application and it can be easily extended to signed number computations.
signed number computations, array multiplier, unsigned numbers, VLSI application, FPGA application, multiplying circuits, Very large scale integration, Silicon compounds, Neural networks, Field programmable gate arrays, Tree data structures, Encoding, Wires
Guoping Wang Dr. (2005).
The Efficient Implementation of An Array Multiplier. Electro Information Technology, 2005 IEEE International Conference on. IEEE.Presented at 2005 IEEE International Conference on Electro and Information Technology, Lincoln, NE.
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